A TLB contains three entries and uses LRU for the replacement policy. Initially, TLB entries are empty. Following is the trace. Note that A,B,C D represent the page numbers of the memory references. Trace: A A B A B C AD CA ABC (a) [5 points] How many TLB misses happen for the given trace? (b) [5 points] Assume no cache misses. What's the total memory access latency for above trace if memory access time is 100 cycles? (c) [5 points] Assume that you only have a single shared L1 cache with a miss rate of 5% and TLB misses and cache misses are not correlated. What's the total memory access latency?