a) To the concept of instruction execution, we must recognize that, in fact, an instruction has a 4+ number of stages. Such a pipelined processor has a clock rate of 2.5GHz and executes a program with 1.5 million instructions. The pipeline has six stages, and instructions are issued at a rate of one per clock cycle. i. Draw a flow chart of six stage "CPU instruction pipeline" depicting the logics necessary for branches and interrupts ii. Ignoring penalties due to branch instructions and out-of-sequence executions what is the speedup of this processor for this program compared to a nonpipelined processor? Show the intermediate calculating steps. iii. What is the pipelined processor's throughput (in MIPS) with the same assumptions? iv. What is pipeline bubble? Provide some instances demonstrating how this event can occur in a variety of ways under the aforementioned circumstances, along with the required figures. b) Assume a disk drive comprises of four drives with a 200GB capacity each. i. Draw a diagram illustrating the mapping between logical and physical disk space for such disk drive. ii. What is the available data storage capacity for each of the RAID levels 0,1,3,4, 5 , and 6