a. Why a fully associative mapped cache memory is expensive?

b. What is a pipeline? Define the speedup of a pipeline (Just define. No need for formulas).

c. What are the types of registers in CPUs?

d. Why a capacity miss occurs in cache memory?

e. What do you think, the DMA controlled or Interrupt driven I/O method is used for data transfer with HDD? Why?

Note: Don't write the question again when you answer. Just label your answers: a. b. c.

Computer Organisation & Architecture