a) Write a Verilog module that implements a 1-bit partial full adder (PFA).

b) Through instantiating the module in a) plus other logic, implement a 4-bit full adder with Verilog.

c) Write a proper test-bench and stimulus, thoroughly test your 4 bit carry lookahead adder.

d) Show a waveform snapshot that indicates you adder can correctly compute 0101 + 1101 and show your results.