ab Description $$ Part I

$1)$ Consider the hypothetical processor with instruction format seen below:

In class, we saw an example that considered three instruction opcodes. For this question,

we add two more for a total of five. They full set of opcodes, in binary, is as follows:

$0001=$ Load AC from memory $0011=$ Load AC from I$/$O device

$0010=$ Store AC to memory $0111=$ Store AC to I$/$O device

$0101=$ Add to AC from memory

For the new opcodes $0011$ and $0111,$ the address field in the instruction refers to some

external I$/$O device. Show the execution for a program that does the following:

$1.$ Load AC from device $5($address $705).$

$2.$ Add contents of memory location $305.$

$3.$ Store AC to device $6($address $706).$

In your answer, it is enough to show the contents of the registers at each step. The initial

state of the CPU, in the same format we saw in class, can be seen in the first fetch stage on

the next page. You must fill in the memory and register values for this initial fetch stage and

all remaining instruction cycles. Use Hexadecimal digits when filling in the stages.

$2)$ Consider the multi$-$level memory profile below:

Level $1$: $1000$ bytes $0\mathrm{.}5$t access time

Level $2$: $1000$ KB $1\mathrm{.}0$t access time

Below what hit ratio is this multi$-$level scheme doing more harm than good? Put another

way, at what hit ratio would we be better off with just level $2$ memory? Refer to the hit

ratio example in the slides to get started.

Fetch stage Execute stage