1. Again using page 61, convert this assembly instruction to binary, and then hex. Hints: $t6 is the "destination," rt. 24 will be represented as a 16-bit number.

    lw $t6, 24($t0) 

MIPS REGISTER ADDRE rsrt YS rd rd shamt funct 000000 01001 01010 01000 00000 100000 add $t0,$t1,$t2 function for add is 32 Figure 6.2 MIPS register addressing. op when op is 0 or 1 the operation is determined by other fields funct rt 000000 - 000001 000010 j 000011 jal 000100-bag) 000101 bne 000110 blez 000111 bgtz 001000 addi 001001 addiu 001010 situ - 001011 sitiu 001100 andi 001101 ori 001110 xori 001111 lui 00000 bitz 00001 bgez 10000 bltzal 10001 bgezal 000000 sll 000001 000010 srl 000011 sra 000100 sllv 000101 000110 srlv 000111 srav 001000 jr 001001 jalr 001010 001011 001100 syscall 001101 break 001110 001111 010000 mfhi 010001 mthi 010010 mflo 010011 mtlo 100000 lb 100001 lh 100010 Iwl 100011 lw 100100 lbu 100101 lhu 100110 lwr 100111 101000 sb 101001 sh 101010 swl 101011 sw 011000 mult 011001 multu 011010 div 011011 divu 100000 add 100001 addu 100010 sub 100011 subu 100100 and 100101 or 100110 xor 100111 nor 101000 101001 101010 slt 101011 sltu Figure 6.3 MIPS instruction opcodes. MIPS REGISTER ADDRE rsrt YS rd rd shamt funct 000000 01001 01010 01000 00000 100000 add $t0,$t1,$t2 function for add is 32 Figure 6.2 MIPS register addressing. op when op is 0 or 1 the operation is determined by other fields funct rt 000000 - 000001 000010 j 000011 jal 000100-bag) 000101 bne 000110 blez 000111 bgtz 001000 addi 001001 addiu 001010 situ - 001011 sitiu 001100 andi 001101 ori 001110 xori 001111 lui 00000 bitz 00001 bgez 10000 bltzal 10001 bgezal 000000 sll 000001 000010 srl 000011 sra 000100 sllv 000101 000110 srlv 000111 srav 001000 jr 001001 jalr 001010 001011 001100 syscall 001101 break 001110 001111 010000 mfhi 010001 mthi 010010 mflo 010011 mtlo 100000 lb 100001 lh 100010 Iwl 100011 lw 100100 lbu 100101 lhu 100110 lwr 100111 101000 sb 101001 sh 101010 swl 101011 sw 011000 mult 011001 multu 011010 div 011011 divu 100000 add 100001 addu 100010 sub 100011 subu 100100 and 100101 or 100110 xor 100111 nor 101000 101001 101010 slt 101011 sltu Figure 6.3 MIPS instruction opcodes