All of the 10 questions below (Q1 through Q10) are in reference to the Design problem in the next paragraph. When you answer all the 10 questions, you will have done the design. Design a circuit that takes in a clock of 100 MHz and produces a clock signal with a period of 50 ns and duty cycle of 40%. The output should be free of glitches. You will be essentially designing a Clock Divider with a particular duty cycle requirement, which is essentially a counter. No need for a reset input.

Q1 5 pts: What is the period of the input clock running at 100 MHz?

Q3 5 pts: What are the inputs and outputs of a positive edge triggered D-type flip-flops? Draw and name them.

Q8 15 pts: Give me the Truth Table (TT) of the Cloud of Logic.

Q5 5 pts: How many states are needed? How many state flops are needed?

Q6 15 pts: Draw the bubble diagram. (The state machine can power up in any state. Therefore, unused states should transition to the designated reset state.) Q7 15 pts: First draw the circuit as a cloud of logic and specific flops, i.e., name the flops and explain the purpose of each. (Flop means positive edge triggered D-type flip-flop.)

Q8 15 pts: Give me the Truth Table (TT) of the Cloud of Logic. Q9 15 pts: Implement the TT using AND2 (i.e., 2-input AND gate), OR2, and INV gates. Draw a circuit schematic. Q10 15 pts: Convert the design of the logic cloud to NAND2 gates. Draw a circuit schematic.