Although the control unit as a whole requires $50$ps$,$ it so

happens that we can extract the correct value of the Reg$2$Loc control wire directly

from the instruction. Thus, the value of this control wire is available at the same

time as the instruction. Explain how we can extract this value directly from the

instruction. Hints: Carefully examine the opcodes shown in Figure $2\mathrm{.}20.$ Also,

remember that LSR and LSL do not use the Rm field. Finally, ignore STXR$.$

$4\mathrm{.}7\mathrm{.}2[5]<4\mathrm{.}4>$ What is the latency of an R$-$type instruction $($i$.$e$.,$ how long must

the clock period be to ensure that this instruction works correctly$)?$

$4\mathrm{.}7\mathrm{.}3[10]<4\mathrm{.}4>$ What is the latency of LDUR? $($Check your answer carefully.

Many students place extra muxes on the critical path.$)$

$4\mathrm{.}7\mathrm{.}4[10]<4\mathrm{.}4>$ What is the latency of STUR? $($Check your answer carefully.

Many students place extra muxes on the critical path.$)$

$4\mathrm{.}7\mathrm{.}5[5]<4\mathrm{.}4>$ What is the latency of CBZ$?$

$4\mathrm{.}7\mathrm{.}6[5]<4\mathrm{.}4>$ What is the latency of B$?$

$4\mathrm{.}7\mathrm{.}7[5]<4\mathrm{.}4>$ What is the latency of an I$-$type instruction?

$4\mathrm{.}17$ Exercises $371$

$4\mathrm{.}7\mathrm{.}8[5]<4\mathrm{.}4>$ What is the minimum clock period for this CPU?