Answer in VHDL please

Rewrite the following VHDL code using one case statement library ieee; use ieee.std_logic_1164.all; entity circuit is port( a, b, c in std_logic; y: out std_logic ): end circuit; architecture RTL of circuit is begin if_proc: process(a,b,c) begin if (a>b) then yc) then yb) then yc) then y