Answer me number 14 please don't use ChatGPT it didn't gave me the right answer thank you hand written

14. Design a JK flip-flop circuit with synchronous inputs using D flip-flops. The circuit should operate as follows: When the clock signal (CLK) is rising edge-triggered, the flip-flop should toggle its state if the J input is 1. If the K input is 1, the flip-flop should reset to 0 regardless of the clock signal. Implement this using D flip-flops and other necessary logic gates. Hint: Design the truth table and show the next state