answer this question please

(c) Consider a processor with 32 bit virtual addresses, 4K-byte pages, and 36-bit physical addresses. Assume el memory is byte-addressable. . LI data cache 32K by 4-byte blocks, 2-way set associative, indexed and tagged with physical address, write-bac . 4-way set associative TLB with 128' entries in all. Assume the TLB keeps a valid bit, a dirty bit, a reference bit, and three permission bits (read, write, execute) for each entry Specify the number of byte offset, index, and tag bits for data cache and the size of each field of a TLB (13) entry