ASSIGNMENT-2 Q1) Design a JK flip flop with behavioral level in verilog. Then simulate it with testbench module. (Take screen shots from your codes and simulation's output) Clk C JK Flip Flop CIK J K Q Q State 1 0 0 0 0 No change in state 1 0 1 0 1 Resets Qto 0 1 1 0 1 0 Sets Q to 1 1 1 1 Toggles 0 1