Assume a pipeline with 5 stages: Fetch Instruction (FI), Decode Instruction(DI), Calculate Address (CA), Fetch Operand (FO), and Execute (EX). Draw a timing diagram for a sequence of instruction (I1, I2, I3, I4, I5, I6, and I17), in which I4 is a branch instruction to I17 that is taken and in which there are no data dependencies.