Assume a processor with a 2GHz clock. The cache has a base cache access time (including hit detection) of 1 clock cycle, and L1 miss penalty of 8 cycles, and an L2 miss penalty of 50 cycles. Assume that 6% of read accesses to the L1 data cache miss and that 25% of read accesses to the L2 miss. What is the average memory access time per load instruction? (State your answer in nanoseconds)