Assume: a register clock-to-Q propagation delay of 0.4 ns . a register setup time of 0.3ns propagation delay of combinational logic 1 of 6 ns propagation delay of combinational logic 2 of 4 ns propagation delay of combinational logic 3 of 3 ns What is the minimum latency of the following circuit? What is the maximum throughput of the following circuit? CLK CLK Combinational Logic 1 Combinational Logic 3 Combinational Logic 2 What is the minimum latency of the following circuit (note the additional register)? What is the maximum throughput of the following circuit? CLK CLK CLK Combinational Logic 1 Combinational Logic 3 Combinational Logic 2 Assume: a register clock-to-Q propagation delay of 0.4 ns . a register setup time of 0.3ns propagation delay of combinational logic 1 of 6 ns propagation delay of combinational logic 2 of 4 ns propagation delay of combinational logic 3 of 3 ns What is the minimum latency of the following circuit? What is the maximum throughput of the following circuit? CLK CLK Combinational Logic 1 Combinational Logic 3 Combinational Logic 2 What is the minimum latency of the following circuit (note the additional register)? What is the maximum throughput of the following circuit? CLK CLK CLK Combinational Logic 1 Combinational Logic 3 Combinational Logic 2