Assume that a processor employs a memory address register (MAR), a memory b register (MBR), a program counter (PC), and an instruction register (IR), supporti only one-address instructions. List the symbolic sequence of micro-operations for interrupt cycle. Assume that a processor employs a memory address register (MAR), a memory b register (MBR), a program counter (PC), and an instruction register (IR), supporti only one-address instructions. List the symbolic sequence of micro-operations for interrupt cycle