Assume that individual pipeline stages of the datapath have the following latencies:

$($a$)(5$ pts$.)$ What is the clock cycle time in a pipelined and non$-$pipelined processor in

each case?

$($b$)(10$ pts$.)$ What is the total latency of an $1w$ instruction in a pipelined and non$-$

pipelined processor in each case?

$($c$)(10$ pts$.)$ If we can split one stage of the pipelined datapath into two new stages, each

with half the latency of the original stage, which stage would you split and what is the

new clock cycle time of the processor for case $($i$)$ and $($ii$)?$

$(15$ pts$.)$ The processor diagram below is the pipelined MIPS datapath we covered in class.

Assume the individual stages of the datapath above have the foloowing latencies