Assume that op is a 2-bit signal with the std_logic_vector data type.consider the following code segment: case op is when 00 => y '0'); when

Assume that op is a 2-bit signal with the std_logic_vector data type.consider the following code segment:

case op is

when "00" =>

y<= (others => '0');

when '01' =>

if (a>0) then

y<=a-1;

else

y<=a+1;

end if;

when others =>

y<=a+b;

end case;

a) draw conceptual diagram

b) rewrite code using concurrent conditional and selected signal assignment statements.