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Assume that the individual stages of MIPS datapath have the following latencies: Your answer should be as the following format: 20Hz, 20MHZ, 20GHZ ...

Assume that the individual stages of MIPS datapath have the following latencies: Your answer should be as the following format: 20Hz, 20MHZ, 20GHZ ... and so on. No spaces in between and the letters are case-sensitive). IF ID EX MEM WB 100ps 100ps 400ps 250ps 150ps What is the clock rate of pipeline architecture in Hz?

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