Assume that the processor has two-level of caches. The L1 hit latency is 1 cycle; the L1 hit rate is 90%; the L2 hit latency is 10 cycles; the local hit rate of the 1MB L2 cache is 80%; and the main memory access latency is 120 cycles.

a. What is the AMAT (Average Memory Access Time)? What is the average memory stall cycle per instruction if every instruction generates 1.4 memory accesses on average?

b. Now assume that the L3 cache is added to improve the performance. The L3 hit latency is 30 cycles. If the L3 local hit rate is 40%, what is the AMAT now? What is the minimum L3 hit rate to make the L3 cache beneficial?

Do show proper formulae and calculations.