Assume the following information:

-The average memory penalty for a cache miss is 72 clock cycles.

-Miss rate is 2.9%

-20% of instruction are data transfer instructions (loads / stores).

-CPI for a perfect cache is 1.5 clock cycles.

-The total number of instructions executed is IC.

Answer the following questions:

A. What is the total number of memory stall cycles?

B. What is the number of Memory Stall Cycles (MSC) per instruction?

C. What is the average CPI?