Assume the following operation times for different MIPS datapath components: Instruction memory: 500 PS, Data memory: 500 PS, ALU: 400 PS, Read or Write to Register File: 300 PS Assume the following instruction mix: 30% ALU, 40% Loads, 20% stores, 10% branches. The maximum frequency at which a Single Cycle design would run at is nearly O 770 MHz 500 MHz O 667 MHz O 590 MHz The maximum frequency at which a Multicycle design would run at is nearly O 4.0 GHz O 2.0 GHz O 2.5 GHz O 3.3 GHz The average CPI of the multi-cycle MIPS is about O 4.1 O 4.3 O 3.8 O 4.2 Assume the following operation times for different MIPS datapath components: Instruction memory: 500 PS, Data memory: 500 PS, ALU: 400 PS, Read or Write to Register File: 300 PS Assume the following instruction mix: 30% ALU, 40% Loads, 20% stores, 10% branches. The maximum frequency at which a Single Cycle design would run at is nearly O 770 MHz 500 MHz O 667 MHz O 590 MHz The maximum frequency at which a Multicycle design would run at is nearly O 4.0 GHz O 2.0 GHz O 2.5 GHz O 3.3 GHz The average CPI of the multi-cycle MIPS is about O 4.1 O 4.3 O 3.8 O 4.2