Assume the following operation times for different MIPS datapath components:

Instruction memory: $500$ ps$,$ Data memory: $500$ ps$,$ ALU: $400$ ps$,$ Read or Write to Register File: $300$ ps

Assume the following instruction mix: $30\%$ ALU, $40\%$ Loads, $20\%$ stores, $10\%$ branches.

The maximum frequency at which a Single Cycle design would run at is nearly

Multiple choice $1$ Question $3$

$667$ MHz

$590$ MHz

$500$ MHz

$770$ MHz

The maximum frequency at which a Multicycle design would run at is nearly

Multiple choice $2$ Question $3$

$3\mathrm{.}3$ GHz

$4\mathrm{.}0$ GHz

$2\mathrm{.}5$ GHz

$2\mathrm{.}0$ GHz

The time it takes to complete the execution of a store operation in Multicycle design is about

Multiple choice $3$ Question $3$

$1700$ ps

$1500$ ps

$2000$ ps

$1600$ ps

The average CPI of the multi$-$cycle MIPS is about

Multiple choice $4$ Question $3$

$4\mathrm{.}1$

$3\mathrm{.}8$

$4\mathrm{.}3$

$4\mathrm{.}2$