Assume the Following operation times for different MIPS datapath components:Instruction memory: $250$ ps$,$ Data memory: $250$ ps$,$ ALU: $200$ ps$,$ Read or Write to Register File: $200$ psAssume the following instruction mix: $30\%$ ALU, $30\%$ Loads, $30\%$ stores, $10\%$ branches.The maximum frequency at which a Single Cycle design would run at is nearly $1100$ MHZO $900$ MHz $770$ MHz $667>$The maximum frequency at which a Multicycle design would run at is nearlyO $5\mathrm{.}0$ GHzO $2\mathrm{.}5$ GHz $4\mathrm{.}0$ GHzO $3\mathrm{.}3$ GHzThe time it takes to complete the execution of a store operation in Multicycle design is aboutO $600$ psO $850$ ps$1100$ ps$900$ psThe average CPI of the multi$-$cycle MIPS is about$04\mathrm{.}3$O $3\mathrm{.}84\mathrm{.}1$