Assume the miss rate of an instruction cache is $4\%$ and the miss rate of the data cache is $6\%.$ The processor has a CPI of $4$ without any memory stalls, and the miss penalty is $100$ cycles for all misses. Assume the frequency of all loads and stores is $40\%$

a$)$ What is the instruction cache miss rate?

b$)$ What is the number of memory$-$stall cycles for data miss in terms of the instruction count$($I$)?$

c$)$ What is the total CPI?

d$)$ Determine how much faster a processor would run with a perfect cache that never missed.