Assume the pipeline architecture of Figure $1$ with floating point instructions following thepipeline of Figure $2.$ Let all memory accesses be zero$-$wait state and assume that half cycleclocking is available for communicating results between general purpose registers during theWB and ID cycles. The units marked $`$ADD$\text{'}$ will perform both addition and subtractionwhereas the $`$ALU$\text{'}$ unit also supports logical operands.All questions refer to the code of Table $1$ in which the initial value for register R$4$ is R$2+792.$ Note that Rx denotes an integer register and Fx a floating point register$\mathrm{.}1.$ Compose a pipeline$-$timing diagram for the case of the code from Table $1$ and dataow of Figure $1($illustrate the first two loops of execution$).$ There is no forwarding orbranch delay slot.$($a$)$ How many clock cycles are necessary to complete execution of all the code associated with a single loop?$($b$)$ On which clock cycle does the second loop commence?$($c$)$ How many clock cycles are executed before the last loop completes execution?$2.$ Now assume that forwarding is available. Compose a pipeline$-$timing diagram for thisscenario and answer the following questions:$($a$)$ How many clock cycles are necessary to complete execution of all the code associated with a single loop?$($b$)$ On which clock cycle does the second loop commence?$($c$)$ How many clock cycles are executed before the last loop completes execution?$3.$ Now assume that both forwarding and a branch delay slot is available. In order tomake use of the branch delay slot you may reorder the instructions, but cannot changeany operands or opcodes. Compose a pipeline$-$timing diagram for this scenario andanswer the following questions:$($a$)$ How many clock cycles are necessary to complete execution of all the code associated with a single loop?$($b$)$ On which clock cycle does the second loop commence?$($c$)$ How many clock cycles are executed before the last loop completes execution?Please make sure for the diagram that you take the instructions as columns and clock cycles as rows

Make sure you check figure $2$ as it states that FP int multiply: M$1,$ M$2,$M$3...$M$7$ and FP adder A$1,$ A$2,$ A$3,$ A$4$ also check the image for table $1$ and for fig $1$