Assume we have a computer where the CPI is $1\mathrm{.}0$ when all memory accesses $($including data and instruction

accesses$)$ hit in the cache. The cache is a unified $($data $+$ instruction$)$ cache of size $256KB,4-$way set

associative, with a block size of $64$ bytes. The data accesses $($loads and stores$)$ constitute $50\%$ of the

instructions. The unified cache has a miss penalty of $25$ clock cycles and a miss rate of $2\%.$ Assume $32-$

bit instruction and data addresses.