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Assume we would like to extend the MIPS architecture to support a larger register file with 256 registers and supporting twice as many instructions. How

  1. Assume we would like to extend the MIPS architecture to support a larger register file with 256 registers and supporting twice as many instructions.
    1. How would this architecture change affect the size of each of the bit fields in an R-type instruction?
    2. How would this affect the size of each of the bit fields in the I-type instruction?
    3. How could each of the two proposed changes decrease the size of a MIPS assembly program?
    4. How could each of the two proposed changes increase the size of a MIPS assembly program?

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