Assuming stall-on-branch and no delay slots, what speedup is achieved on this code if branch outcomes are determined in the ID stage, relative to the execution where branch outcomes are determined in the EX stage? The remaining problems in this exercise assume that individual pipeline stages have the following latencies: IF: 150ps ID: 200ps EX: 200ps MEM: 200ps WB: 100ps

Instruction Sequence: SW R2, 0(R3) OR R1, R2, R3 BEQ R2, R0, Label ;Assume R2 == R0 OR R2, R2, R0 Label: ADD R1, R4, R3