Assuming we have a pipeline of $7$ stages:

Instruction Fetch $-$ The instruction is fetched from instruction registers, or cache, or memory.

Instruction Decoder $-$ The instruction is decoded.

Instruction Issuing Queue$-$ A queue here stores the instructions. The registers are renamed when necessary.

Operands Fetch$-$ The operands are fetched from the data registers. The instruction shall wait, if it has a dependency, in a reservation station until its source operands have valid status and a suitable ALU is available.

Execution$-$ When both source operands are ready and a suitaile ALU is available, then execution begins.

Write Back$-$ When the assigned functional unit completes its execution, the result is written back to the designated register $($or the renamed register if there is a renaming$).$

Commitment$-$ The result is copied from the renamed register to the designated register.