(b) Compute the miss penalty to transfer 8 words cache block from DRAM, where i takes 2 memory bus cycles to send the address, 25 memory bus cycles for DRAM access time and 3 memory bus cycles to send one word of data for the following three organizations (i) One- word-wide memory organization, ii) Wide memory organization (4-word wide) and i) Interleaved memory organization (4 banks). Show all your work to get full credit