(b) Consider a pipelined processor, where the pipeline stages are F (fetch), D (decode), R (register read), E (execute) and W (write back). Describe what happens in the pipeline stages for the var- ious types (data movement, data processing, control) of instruc- tions (c) Show the execution of your program on the above pipelined pro- cessor for k -5 by drawing a diagram. Assume that the fetched and decoded instructions are stored in an instruction window IW with a capacity of 12 instructions, and that there is no resource conflict between fetching instructions and executing data transfer nstructions. Explain where and why delav slots appear (b) Consider a pipelined processor, where the pipeline stages are F (fetch), D (decode), R (register read), E (execute) and W (write back). Describe what happens in the pipeline stages for the var- ious types (data movement, data processing, control) of instruc- tions (c) Show the execution of your program on the above pipelined pro- cessor for k -5 by drawing a diagram. Assume that the fetched and decoded instructions are stored in an instruction window IW with a capacity of 12 instructions, and that there is no resource conflict between fetching instructions and executing data transfer nstructions. Explain where and why delav slots appear