(b) Fill in the following blanks in the following snippet of Verilog on the dotted lines (cg. so that out matches the output of a 2-to-1 mux with inputs a and b, and a select bit, sel, equal to AND(c,d). Each blank should have one word or symbol. module mux2tol( Lnput a, b, d, d, output always (d) begin if (sel) out else out