Based on the given CU+DU and ASM of the bit counter, fill in the timing diagram in Fig. Q.5(a). Assume data=0101 at all times during the simulation (10 marks) clock data 0101 st load en_sh a0 zero en_ct done XX 0000 B xx 00 Fig. 0.5(a) Based on the given CU+DU and ASM of the bit counter, fill in the timing diagram in Fig. Q.5(a). Assume data=0101 at all times during the simulation (10 marks) clock data 0101 st load en_sh a0 zero en_ct done XX 0000 B xx 00 Fig. 0.5(a)