Based on the MIPS architecture and control tables below, answer the following questions: Intr. opcode LW SW J BEQ R-type R-type 10 R-type 10 R-type 10 R-type 0000 ALUOP 0001 00 0010 00 01 10 ALUControl 10 X Function AND OR add Instruction operation load word store word branch equal add subtract AND OR set on less than jump 0110 0111 Funct field 1100 XXXXXX XXXXXX XXXXXX 100000 100010 100100 100101 ALUControl 101010 XXXXXX Desired ALU action add add NOR subtract add subtract AND OR set on less than X Function subtract set on less than R-type instruction Field 0 Bit Position 31:26 lw/sw instruction format Field 35 or 43 Bit Position 31:26 addi instruction format PC 4 Field 8 rs Bit Position 31:26 25:21 Add nd Instr. Addr [51:01 Instruction Memory 25:21 rs 25:21 PC+4 rs 31:26 25:21 20:16 15:11 15:0 20:16 20:16 rt 20:16 Regist MUX Main ALUOP Decoder Mete ALUSIE 5:0 A1 AZ A3 Register File WD3 Begonte Sign Extend ADI BD2 32 rd 15:11 10 shamt 10:6 address 15:0 1 MUX address 15:0 ALU De der Zere ALU NU ALUControl Funct 5:0 Addr Read Data Data Memory Write Data 0 MUX 1 Fill the control bits for each instruction in the table below. (Hint: If a control bit is not important, put x in its field) Instruction RegDst RegWrite MemRead MemWrite Mem ToReg ALUOP ALUSrc addi sub lw SW