Basic Requirements -

*Using the image below....

? C++ code.

? All developed code should be object oriented and should meet the requirements outlined below.

? External libraries may be used to implement components like threading and file management, etc.; however, all queue components should be developed according to the image above (i.e. a FIFO queue should be used to read in the initial packet file data and a priority queue should be used for the VLAN priority queues).

Important Note: Thread 1 components(blue boxed area)should be completed using knowledge from your ADS course, whereas threads 2 and 3 (green and orange, respectively) will require knowledge from your OS course

Detailed requirements -

1. Set up thread 1 for processing incoming packets. This thread should perform the following steps:

a. Sequentially read packets from the provided packet file into a FIFO (first in, first out) queue for processing. (Step 1)

b. Read packets sequentially from the FIFO queue and redirect them into one of two priority queues based on their VLAN tag and priority number (802.1Q). (Step 2)

i. First, read the packet popped off the FIFO queue and determine its VLAN number by inspecting the packets 802.1Q tag.

ii. Next, determine which destination interface queue the packet needs to be inserted into (one priority queue should be created for VLAN 100 and another for VLAN 101).

iii. Once you have determined the destination queue, inspect the packets 802.1Q priority value and insert it into the correct destination queue. (Step 3)

1. A priority value of 0 indicates best effort and should be inserted into the destination queue based on its time of arrival (i.e. it should be added to the end of the queue)

2. A priority value of 2 indicates a excellent effort priority and should be inserted in front of existing packets in the queue based on its time of arrival (i.e. it should be inserted ahead of priority 0 packets, but should not be put ahead of already queued priority 2 packets).

iv. If a priority 2 packet has been detected, a notification and copy of the packet should be sent to the threaded interrupt handler (thread 2). (Step 2.5)

c. Once all packets have been inserted into the correct interface queues, this thread should terminate.

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2. Set up thread 2 for processing incoming priority packet interrupts. This thread should perform the following steps:

a. Priority packet interrupts should be received as a copy of the original packet.

b. For each priority packet interrupt, a new child thread should be created to log an alert to both a log file and the screen. This thread should be given an object containing information about the packet (i.e. source MAC and destination MAC) and a timestamp of when the interrupt was received. (Step 3.5)

c. A lock should be created to control which threads are able to write to the log file and the screen. A thread should only be able to write to the log file and screen if it has access to the lock. When a thread is given the lock, it should 9 write an alert to the log file and screen stating that a priority packet was received and should include information about the packets destination and source MAC address. (Step 4.5)

i. Ultimately the result should be that threads log priority packet alerts to the log file and screen in the order of arrival. If the lock handling mechanism is not implemented properly, a race conditional will occur causing threads to write to the log file and screen in an unpredictable fashion.

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3. Set up thread 3 for printing queued packets to the screen and logging them to the log file. This thread should perform the following steps:

a. All packets processed by this thread need to be outputted to the same screen used by thread 2 and the same log file used by thread 2.

b. Every 1 second, a packet should be read from the front of interface #1s priority queue (VLAN 100) and removed from its queue. (Step 4)

i. The thread should then wait to have access to the lock used to control writing to the log file and screen.

ii. Once the lock is obtained, the thread should write the packets contents to the log file (source and destination MAC + payload contents) and to the screen.

iii. After the log and screen operation has been completed, the lock should be released.

c. Immediately after, a packet should be read from the front of interface #2s priority queue (VLAN 101) and removed from its queue. (Step 4)

i. The thread should then wait to have access to the lock used to control writing to the log file and screen.

ii. Once the lock is obtained, the thread should write the packets contents to the log file (source and destination MAC + payload contents) and to the screen.

iii. After the log and screen operation has been completed, the lock should be released.

d. This thread should sleep for 1 second and then loop to continue processing the queued packets until both queues are empty. Once both queues have been emptied, the thread should terminate.

Legend Slep 45 Log Priority Packet in order of Antal and Output Screen Screen Output Read Packet From Queues Priore Patternut Handet Soreen and write to Log File in Comed Order MAN 100 Priority Que MAN 101 Proty Queue Packet 2 (Priority 2) Packet 4 (Priority 2) Packet 5 (Priority 2) Packet 1 Priority) Insert Packet into Linked List Priority Queue Based on Priority Number (802.1Q) and Time of Packet 3 Priority 0) Packet 6 (Priority 0) Step 2.5: Send Notification of Priority Packet to Handler Step 2: Redirect Packets Based on VLAN Number in Packet Header onano indu Odla Step 1: Read packets sequentially into FIFO queue Figure 1. Switching Project Overview Legend Slep 45 Log Priority Packet in order of Antal and Output Screen Screen Output Read Packet From Queues Priore Patternut Handet Soreen and write to Log File in Comed Order MAN 100 Priority Que MAN 101 Proty Queue Packet 2 (Priority 2) Packet 4 (Priority 2) Packet 5 (Priority 2) Packet 1 Priority) Insert Packet into Linked List Priority Queue Based on Priority Number (802.1Q) and Time of Packet 3 Priority 0) Packet 6 (Priority 0) Step 2.5: Send Notification of Priority Packet to Handler Step 2: Redirect Packets Based on VLAN Number in Packet Header onano indu Odla Step 1: Read packets sequentially into FIFO queue Figure 1. Switching Project Overview