Below Diagram shows a FIFO with separate RdClk and WrClk$,$ both these clocks are of the same frequency $($F$),$ but they are not synchronous.

There is a variation of $+/-$ X$\%$ in time periods as compared to base frequency $($F$).$

The WrReq supports a burst of writes, and data is written to the FIFO in back to back clock cycles during a burst. The RdReq is asserted every clock cycle as long as there is valid data in the FIFO.

FIFO Depth N $=4$

Frequency is $100$MHz

Clock Frequency Variation is $20\%$

what is the maximum WrReq burst length?