Branching Prediction

In this assignment you will design a branch predictor using the Verilog hardware description language. You will need to use a tournament predictor in your design. A tournament predictor $(-$ing., Tournament Predictor$)$ makes predictions by evaluating the results of multiple branch prediction algorithms. Which predictor's result will be used is stored in a confidence table. The tournament predictor you design should use the GShare predictor $[1]$ and the Perceptron predictor $[2].$

You will write your design in a verilog file called tournament.v$.$ You can imagine that this module will be put into the fetch stage of a pipelined processor. The fetched command and program counter are given to your predictor module in the Fetch phase. Your module

skips or does not skip the branch result. During the execution phase of the pipeline, the branch orders are finalized and the information of these results is passed back to your module. By looking at these results you can understand whether your prediction was right or wrong and improve your future predictions. Your tournament module calls two different predictor modules. Your first predictor uses the GShare algorithm $($gshare$.$v$),$ your second predictor uses the Perceptron algorithm $($perceptron$.$v$).$ Your tournament module uses a confidence table of two$-$peaked counters to decide which predictor to choose. Accesses to the table are made using some bits of the PS$.$ Each entry of the table consists of a two$-$peaked counter. The state machine of the table is as follows. The counter is updated according to whether the selected predictor predicts correctly or not.The input$/$output signals of the $3$ modules you will design should be as follows.

tournament.v

module name: tournament

Parameters

GT$\_$BIT: Specifies the number of bits to access the trust table. The GT$\_$BIT bit after the $2$ most meaningless bits of the program counter is used to address the trust table. The size of the trust table must depend on GT$\_$BIT.

GSHARE$\_$BIT: Sets the submodule parameter.

PERCP$\_$BIT: Sets the sub$-$module parameters.

WEIGHT$\_$BIT: Determines the sub$-$module parameter. inputs:

clk $(1$ bit$)$: Clock input

rst $(1$ bit$)$: Signal to return the predictor to initial state

fetch$\_$ps $(32$ bits$)$: Address of the command to be branch predicted

fetch$\_$order $(32$ bits$)$: The command to be branch predicted

fetch$\_$valid $(1$ bit$)$: indicates that the $$fetch$\_*$ signals in that cycle are valid. You only need to predict in cycles where this input is $1.$

yurut$\_$ps $(32$ bits$)$: Address of the resulting command

yurut$\_$command $(32$ bit$)$: Resulting command

yurut$\_$branch $(1$ bit$)$: Branching result of the resulting command

yurut$\_$dallan$\_$ps $(32$ bits$)$: Address to skip if the result is skips

yurut$\_$valid $(1$ bit$)$: indicates that the $$yurut$\_*$ signals in that cycle are valid. When this input is only $1,$ you should use the $$yurut$\_*$ signals to update your branch predictor.

outputs

result$\_$wave $(1$ bit$)$: Prediction result $(0->$ does not jump, $1->$ jumps$)$

result$\_$predictor $(1$ bit$)$: Indicates which predictor made the prediction $(0->$ GShare, $1->$ Perceptron$).$

gshare.v

module name: gshare

Parameters

GSHARE$\_$BIT: Specifies the number of bits of the general history register. The GSHARE$\_$BIT bit after the $2$ least significant bits of the program counter is XORed with the general history register to form the address to access the branch history table. The size of the branch history table must depend on GSHARE$\_$BIT.

inputs and outputs:

same as for the tournament module $($except for result$\_$ongorer$)$

perceptron.v

module name: perceptron

Parameters

PERCP$\_$BIT: Sets the number of bits of the general history register. The PERCP$\_$BIT bit after the $2$ most meaningless bits of the program counter is XOR with the general history register to form the address to access the perceptron table. The size of the perceptron table must depend on PERCP$\_$BIT. The total number of weights is PERCP$\_$BIT $+1.$

WEIGHT$\_$BIT: Determines how many bits each weight has. inputs and outputs:

same as for the tournament module $($except for result$\_$ongoer$)$

You can assume that all orders entering your module are branch orders. You should do the branch prediction combinatorially $($result$\_$dallan and result$\_$dallan$\_$ps should be for fetch$\_$ps and fetch$\_$order in the same cycle$).$