Design and implement in Verilog ( gate level modeling ) a 4 bit ALU according to the following specifications Build a 1 bit ALU for bits 0 to 2 (without the SET line, but including the LESS input) as described in class Your 1 bit ALU is to do ADD, SUBTRACT, AND and OR Use good hierarchical design (through modules in Verilog) Build a 1 bit ALU for the most significant bit (bit 3), including the SET line, as described in class Again, use good hierarchical design Build a 4 bit ALU by instantiating four 1 bit ALU's, as described in class The first three 1 bit ALU's will be instances of the ALU described in item 1 The fourth 1 bit ALU will be an instance of the ALU from item 2 Your 4 bit ALU is to do ADD, SUBTRACT, AND, OR, and SLT (Set On Less Than) Use good hierarchical design and create a separate module for the 4 bit ALU Implement the Overflow and Zero outputs of the 4 bit ALU The overflow may be set only for arithmetic functions (i e should be always 0 for the logic functions) Test the 4 bit ALU by adding a test module in Verilog Make sure to include in the test sequence a few typical examples for each function, including Overflow and Zero Implement two additional functions Arithmetic shift right by 1 bit, and Rotate left by 1 bit These operations should apply to one of the ALU inputs (a) Include a text description, a logic diagram and test results The report should include Descriptive text (ALU functions, function codes, inputs and outputs) and logic diagrams for each circuit described in items 1 3 above Use block level diagrams for the adders and multiplexers In the logic diagrams label each module I O with the variable name used in the Verilog code Verilog source code of all modules including the test module Simulation results (output from running the compiled Verilog code with the test module) The simulation should show the performance of the ALU for all 5 functions(ADD, SUBTRACT, AND, OR, and SLT) For this purpose include a copy of the test module output for each function showing a few typical examples of I O, including Overflow and Zero Label all inputs and outputs and print the data inputs and outputs in both binary and signed decimal format

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gate-level modeling

Build a 1-bit ALU for bits 0 to 2 (without the SET line, but including the LESS input) as described in class. Your 1-bit ALU is to do ADD, SUBTRACT, AND and OR. Use good hierarchical design (through modules in Verilog).
Build a 1-bit ALU for the most significant bit (bit 3), including the SET line, as described in class. Again, use good hierarchical design.
Build a 4-bit ALU by instantiating four 1-bit ALU's, as described in class. The first three 1-bit ALU's will be instances of the ALU described in item 1. The fourth 1-bit ALU will be an instance of the ALU from item 2. Your 4-bit ALU is to do ADD, SUBTRACT, AND, OR, and SLT (Set On Less Than). Use good hierarchical design and create a separate module for the 4-bit ALU. Implement the Overflow and Zero outputs of the 4-bit ALU. The overflow may be set only for arithmetic functions (i.e. should be always 0 for the logic functions).
Test the 4-bit ALU by adding a test module in Verilog. Make sure to include in the test sequence a few typical examples for each function, including Overflow and Zero.
Implement two additional functions: Arithmetic shift right by 1 bit, and Rotate left by 1 bit. These operations should apply to one of the ALU inputs (a). Include a text description, a logic diagram and test results

The report should include:

Descriptive text (ALU functions, function codes, inputs and outputs) and logic diagrams for each circuit described in items 1-3 above. Use block-level diagrams for the adders and multiplexers. In the logic diagrams label each module I/O with the variable name used in the Verilog code.
Verilog source code of all modules including the test module.
Simulation results (output from running the compiled Verilog code with the test module). The simulation should show the performance of the ALU for all 5 functions(ADD, SUBTRACT, AND, OR, and SLT). For this purpose include a copy of the test module output for each function showing a few typical examples of I/O, including Overflow and Zero. Label all inputs and outputs and print the data inputs and outputs in both binary and signed decimal format.