build me a verilog testbench for this REGISTER$($Address$,$ Out$)$;

input $[11$:$0]$ Address;

output reg $[11$:$0]$ Out;

always @$(*)$ begin

Out $<=$ Address;

end

endmodule

$//------------------$

module SourceMemory$($Data$,$ Address, CS$)$;

output reg $[15$:$0]$ Data;

input$[11$:$0]$ Address;

input CS;

reg $[11$:$0]$ ROM$[4095$:$0]$;

always @$($negedge CS$)$

begin

for$($integer i$=0$;i$<4096$;i$=$i$+1)$

begin

ROM$[$i$]=$i;

end

Data$=$ROM$[$Address$]$;

end

endmodule

$//---------------$

module RecievingMemory $($Address$,$Data,CS$)$;

input $[11$:$0]$ Address;

input $[15$:$0]$ Data;

input CS;

reg $[15$:$0]$ ROM$[4095$:$0]$;

always @ $($negedge CS$)$ begin

ROM$[$Address$]<=$ Data;

end

endmodule

$//---------------$

module ERRBLCK$($Datain$,$ Dataout, CLK$)$;

input Datain, CLK;

output reg Dataout;

reg rand;

always @$($negedge CLK$)$ begin

rand $=$ $random;

if $($rand $\%2==0)$ begin

Dataout $<=$ Datain;

end else begin

Dataout $<=$ ~Datain;

end

end

endmodule;

$//----------------$

module transmitter $($SrcReg$,$DBusIN,ACK,Full,CLK$,$Parity,D$15,$Req,DataOut,AddressBus$)$;

input $[11$:$0]$ SrcReg;

input $[15$:$0]$ DBusIN;

input ACK, Full, CLK;

output reg Parity, D$15,$ Req;

output reg $[14$:$0]$ DataOut;

output reg $[11$:$0]$ AddressBus;

reg counter;

integer i;

always @$($negedge CLK$)$ begin

AddressBus $<=$ SrcReg;

if $($Full $==1)$ begin

$finish;

end else if $($ACK $==1)$ begin

AddressBus $<=$ AddressBus $+1\text{'}$b$1$;

end

Parity $<=0$;

counter$<=0$;

for$($integer i$=0$; i$<15$;i$++)$ begin

if$($DBusIN$[$i$]==1)$counter$+=1$;

end

if$($counter$\%2==1)$ Parity$=1$;

Req $<=1$;

for $($i $=0$; i $<15$; i $=$ i $+1)$ begin

DataOut$[$i$]<=$ DBusIN$[$i$]$;

end

D$15<=$ DBusIN$[15]$;

end

endmodule

$//-----------------$

module receiver $($Destreg$,$D$15,$DATAI,Parity,REQ,CLK$,$ACK,full,AddressBUS,DataBus$)$;

input $[11$:$0]$ Destreg;

input D$15$;

input $[14$:$0]$ DATAI;

input Parity;

input REQ;

input CLK;

output reg ACK;

output reg full;

output reg $[11$:$0]$ AddressBUS;

output reg $[15$:$0]$ DataBus;

always @$($posedge CLK$)$ begin

AddressBUS $=$ Destreg;

if $($REQ $==1)$ begin

if $($AddressBUS $==4096)$ begin

full $=1$;

$finish;

end

if $(^\{$D$15,$ DATAI$\}==$ Parity$)$ begin

ACK $=1$;

AddressBUS $<=$ Destreg $+1$;

end

end

for $($integer i $=0$; i $<15$; i $=$ i $+1)$ begin

DataBus$[$i$]=$ DATAI$[$i$]$;

end

DataBus$[15]=$ D$15$;

end

endmodule

$//-------------------$

module TopLevel $()$;

input $[11$:$0]$ Address;

wire $[11$:$0]$ Out;

wire $[15$:$0]$ Data;

input $[15$:$0]$data;

input $[11$:$0]$ SrcReg;

input $[15$:$0]$ DBusIN;

wire $[14$:$0]$ DataOut;

wire $[11$:$0]$ AddressBus;

input $[11$:$0]$ Destreg;

input $[14$:$0]$DATAI;

wire $[15$:$0]$ DataBus ;

REGISTER r$1($Address$,$ Out$)$;

REGISTER r$2($Address$,$ Out$)$;

SourceMemory m$1($Data$,$ Address, CS$)$;

RecievingMemory m$2($Address$,$Data,CS$)$;

ERRBLCK err$($Datain$,$ Dataout, CLK$)$;

transmitter t$1($SrcReg$,$DBusIN,ACK,Full,CLK$,$Parity,D$15,$Req,DataOut,AddressBus$)$;

receiver re$1($Destreg$,$D$15,$DATAI,Parity,REQ,CLK$,$ACK,full,AddressBus,DataBus$)$;

endmodule;