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C.9) Consider the the following block diagram for a 4-bit shift register that also supports clear and parallel load. When the Load control line is asserted and the device is clocked, data present on the D inputs is loaded into the register. If the Load control line is not asserted and the device is clocked, data in the register shifts right (data at the shift-in input is brought in to the MSb). When the Clr control line is asserted, the register is cleared without needing a clock. D Load Shift in a Cir a) What is the difference between a synchronous and an asynchronous control? b) What kind of controls are Load and Cir? c) Show how to construct the device represented by the above block diagram using D flip-flops and Muxes