Cache block size (B) can aect both miss rate and miss latency. Assuming a machine with a base CPI of 1, and an average of 1.35 references (both instruction and data) per instruction, nd the block size that minimizes the total miss latency given the ollowing miss rates for various block sizes.

8: 4%

16: 3%

32: 2%

63: 1.5%

128: 1%

a.) What is the optimal block size for a miss latency of 20 B cycles?

b.) What is the optimal block size for a miss latency of 24 + B cycles?

c.) For constant miss latency, what is the optimal block size?