Cache Memory

loop: addi beq Iw Iw lw addi j $t0,$0,5 $t0,$0, done $t1, OxA4($0) $t2, OxAC($0) $t3, 0xA8($0) $t0, $t0, -1 loop done: 3. (5 points: With 3 or more errors you get 0 points. Otherwise full point.) Consider the above MIPS code segment. The cache capacity is 8 words, block size is 1 word. N= 2. The block replacement policy is LRU. a. In the following table indicate the type of miss, if any: Compulsory, Conflict, Capacity. Instruction Iteration No. 3 1 2 4 5 Ib $t1, OxA4($0) lb $t2, OxAC($0) Ib $t3, OxA8($0) b. How many bits are needed for the implementation of LRU policy: for a set, for the entire cache memory? What is the total cache memory size in number of bits? Include the V bit and the bit(s) used for LRU in your calculations. Show the details of your calculation. C. State the number of AND and OR gates, EQUALITY COMPARATORs and MULTIPLEXERs needed to implement the cache memory. No drawing is needed