Can somebody please help me translate this VHDL code into VERILOG code? Thank you so much.

1Vhd1 Lab 11brary ieee: 3 use ieee.stdlogic 1164.all: entity LAB7 is port (ReaetN, Clock, Coini, Coin2: in atd logic: Bottle, Returnos, Return10: out std logic) end LAB: architecture arch LAB7 of LAB7 i5 10 ype state type is (S00, S05, S10, 315, 820, S25, 330, 335, S40, 845, S50, 355, S60, 865, 370, ROSA, ROSB, R10, R10B, RB): ignai STATES: STATE Eype 12 ignal coin: std logic_vector (1 dovnto 0) 13 Ebegin 15 process (ResetN, Clock) begin 16 17 if (Re3etN-'0') then STATES "S00: 18 elsit (Clock' event and Clock-'1' then 19 case (STATES) is vhen S00 if (Coin 0 then S elsif (coin "01") then elsif(coin10") then else end if: STATES-SO0 STATES805: STATESS10: STATES-S2S: 25 2 6 if (Coin0 then S elsif (coin "01") then elsif(coin10") then STATES-SOS: 28 E 29 E 30 E 3 1 32 STATES <. statess15: states end if: vhen s10 if then elsif elaif else s15> if (Coin "00 then S elsif (coin"O1") then elsif (coin10") then STATESS10 34 E STATES915 STATESS20 STATES-S35; 37 STATES-S15: 40 E STATES320: STATES