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Can someone explain the loop on the right, please? I understand the left one which followed the stall instruction from the green bubble of the

Can someone explain the loop on the right, please? I understand the left one which followed the stallimage text in transcribed instruction from the green bubble of the top.

LD -> any 1 stall FPALU -> any: 3 stalls FPALU ->ST: 2 stalls IntALU - BR 1 stall Smart Schedule Loop: L.D FO, 0(R1) stall ADD.D F4, FO, F2 stall stall S.D F4, O(R1) DADDUI R1, R1,#-8 stall BNE R1, R2, Loop stall Loop: L.D FO, 0(R1) DADDUI R1, R1,#-8 ADD.D F4, FO, F2 stall BNE R1, R2, Loop S.D F4, 8(R1) By re-ordering instructions, it takes 6 cycles per iteration instead of 10 We were able to violate an anti-dependence easily because an immediate was involved Loop overhead (instrs that do book-keeping for the loop): 2 Actual work (the ld, add.d, and s.d): 3 instrs Can we somehow get execution time to be 3 cycles per iteration? 19

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