Can you help me on the following question

Q4: (a) Write a Verilog RTL module that does the following. It has "clock" and "reset" inputs and a 1-bit output port called "out". Clock has a frequency of 50 MHz. Port out is supposed to be a signal with 5 MHz frequency with 30% duty cycle and should have no glitches. (b) Draw waveforms of clock, reset, and out between 0 ns and 160 ns. The clock signal makes its first posedge at O ns. The reset signal starts at value of O and makes a pulse between 1 ns and 21 ns