CISC 260 Machine Organization and Assembly Language (Spring, 2018) Assignment # 3 (Due: March 13. 2018 The following instruction set is supported by a simple processor, which is similar to what we discussed in the class, with a few new instructions added. The format of most instructions is defined as follows. 9 8:6 5:32:0 ode wsrc1src2 dst field unused where the fields are defined as follows. opcode operation to be performed by the processor write back ALU output to register file (1 = yes, 0 = no) address of the first ALU operand in the register file address of the second ALU operand in the register file address in the register file where the output is writtein SIc SIc dst: For opcodes BEQ, BLEZ and JUMP, the 6 least significant bits (5:0) give an address in the instruction memory, which is byte-addressed. The opcode HALT has all operand bits (9:0) being 0. When an instruction has only two operands, the field for the unused operand is filled with 0-bits. For example, bits (5:3) for SLL are all zero because src2 is not used. The opcode and meaning of these instructions are listed in the following table encoding ation ADD SUB SLL SRL INV XOR OR AND INCR BRZ BLEZ 0x0 0x1 src 11-RIsrc2]-> Rldst src1]1 0x4 --RIsrc11 Rldst 0x6 0x7 0x8 0x9 src2] RIdst sTc src 11 & RIsrc2] -> Rldst Src1 If RIsrc 1] = 0, branch to BAddr If R[srcl] 0, branch to BAddi JUMP HALT 0xE 0xF Jump to JAddr Stop execution In this part you are asked to recognize what a given segment of machine code does, by translating it into assembly code, and annotating it with expressions in a high level language like C. This process, 1