Clock Instruction i Instruction Instruction Instruction Fetch Decode Execution Instruction i + 1 Instruction Instruction Instruction Fetch Decode Execution Instruction i + 2 Instruction Instruction Instruction Fetch Decode Execution Suppose a pipeline processor has three stages, as shown in the Figure above. Assume in a perfect scenario... (1) How many clock cycles does it take to execute 10 instructions? Blank (1) Answer (2) What is the throughput in terms of instructions per cycle? (up to 2 sig figs) Blank (2) Answer (3) How many clock cycles does it take to execute n instructions? Blank (3) Answer (4) If n is sufficiently large, what is the throughput in terms of instructions per cycle? Blank (4)