Code the logic of the following equations in RTL Verilog:

acc0 acc1 out

acc1 + in1; acc0 + in2;

acc0 + acc1;

where in1 and in2 are two 32 bit inputs, out is a 40 bit output, and acco and acc1 are two 40 bit internal registers. At every positive edge of a clock the inputs are fed to the design and out is produced.