Columbia College ancouver, Canads 1. For a direct mapped cache design with 32-bit address, the following bits of the address are used to access the cache: Index Byte offset 31-10 9-4 3-0 a) What is the cache line size in bytes? b) How many entries does the cache have? c) What is the ratio between total bits required (data, tag, and valid bits) over the data storage bits? Starting from power on (empty cache), the following byte addressed cache references are recorded: Address #1>0 Address #2>4 Address #3> 16 Address #4>132 Address #5> 232 Address #6>160 Address #7>1024 Address #8>30 Address #9> 140 Address #10> 3100 Address #11> 180 Address #12> 2180 d) How many blocks are replaced? e) What is the hit ratio? f) List the final state of the cache, with each valid entry represented as a record of